`include "common.svh"
module itcm #(
    parameter AW = $clog2(`IRAM_SIZE)
) (
    input clk,
    // IRAM Req
    output req_ready,
    input req_valid,
    input IRAM_Req req,
    // IRAM Rsp
    output IRAM_Rsp rsp
);

  logic[31:0] mem[`IRAM_SIZE/4];

  assign req_ready = 'b1;
  wire req_fire = req_ready & req_valid;
  localparam IRAM_RSP_SIZE = $size(IRAM_Rsp);
  IRAM_Rsp rsp_next;


  generate
    genvar gi;
    for (gi = 0; gi < `IRAM_WIDTH; gi = gi + 1) begin : IRAM_BANK
      wire [AW-1:2] raddr = req.pc[AW-1:2] + gi;
      assign rsp_next.inst[gi] = mem[raddr];
    end
  endgenerate

  initial $readmemh(`ITCM_IMAGE, mem);

  reg_l #(IRAM_RSP_SIZE) rsp_r (
      .load(req_fire),
      .din (rsp_next),
      .dout(rsp),
      .*
  );

endmodule
